A communication system between a plurality of circuits or functional blocks operating with different clock frequencies mainly includes a synchronous system and an asynchronous system. The synchronous system can be applied when a frequency ratio of each clock of two circuits that communicate with each other is one to an integer (e.g., 1:2, 1:3, . . . etc) or an integer to one (e.g., 2:1, 3:1, . . . etc), and phases of the two clocks are equal to each other. In short, the synchronous communication on the basis of the synchronous system is the communication method that can be performed only between the circuits having clocks synchronized with each other.
FIG. 10 shows an example of a semiconductor device in which a circuit A operating with a clock A and a circuit B operating with a clock B communicate with each other using the synchronous system. In this example, the circuit A and the circuit B communicate data from the circuit A to the circuit B using a communication request signal Req, a communication response signal Ack, and a communication data signal Data.
The frequency of the clock A is an integral multiple (e.g., once, twice, three times, . . . etc) of the clock B. The distribution delay of the clock A and that of the clock B are designed to be made equal by a method such as a clock tree synthesis. Further, the timings of the clock A and the clock B are designed so as to satisfy the set up and hold time constraints by adjacent communication timings.
The communication request signal Req is a signal output by the circuit A at the timing of the clock A and received by the circuit B at the timing of the clock B when there is a communication request from the circuit A to the circuit B. The communication response signal Ack is a signal output by the circuit B at the timing of the clock B and received by the circuit A at the timing of the clock A when the circuit B is in a reception possible state or the circuit B normally receives communication data output from the circuit A. The communication data signal Data is a signal that transmits the communication data from the circuit A to the circuit B.
A counter circuit 100 refers to a frequency ratio information 101 indicating a frequency ratio of the clock A to the clock B, and generates a communication timing signal 102 indicating the timing at which the circuit A communicates. The circuit A receives the communication timing signal 102 and makes the communication speed coincide with the reception speed of the circuit B, so as to achieve synchronous communication.
FIG. 11 is a timing chart showing an operation in a case in which the frequency of the clock A is twice as large as that of the clock B, and data is transmitted from the circuit A to the circuit B. This timing chart shows the clock A, the communication timing signal 102, the communication request signal Req, the communication data signal Data, the clock B, and the communication response signal Ack. In FIG. 11, the timings of rising edges of the clock A are indicated by symbols T0, T1, T2, . . . .
Since the frequency of the clock A is twice as large as the frequency of the clock B, the phases (rising edges) of the clock A and the clock B match once for two cycles of the clock A, specifically, at timings T0, T2, T4, T6, T8. The circuit A refers to the communication timing signal 102 that indicates the timing at which the phases of the clock A and the clock B match to perform communication operation only at a timing at which the phases of the clock A and the clock B match. On the other hand, the circuit B performs the communication operation for each cycle of the clock B. Thus, the communication speed of the circuit A coincides with that of the circuit B.
More specifically, the communication timing signal 102 has the value 1 at a timing at which the phases of the clock A and the clock B match and communication is performed. Flip-flops A1, A2, and A3 included in the circuit A each have an enable input (EN) that receives the communication timing signal 102, so as to operate only at a timing at which the communication timing signal 102 has the value 1. Hence, the circuit A outputs the communication request signal Req and the communication data signal Data and receives the communication response signal Ack at a timing at which this communication is performed.
When the frequency of the clock A is an integral multiple of the clock B, the communication timing signal 102 can be easily generated by the counter circuit 100. For example, when the frequency of the clock A is N times as large as the clock B (N is an integer), the value 1 may be output as the communication timing signal 102 once for N cycles using a count circuit that counts up from 1 to N.
Next, a specific communication operation will be described with reference to FIG. 11. First, at timing T0, the circuit A outputs the value 0 as the communication request signal Req, so as to notify the circuit B that there is no communication request. On the other hand, the circuit B outputs the value 1 as the communication response signal Ack, so as to notify the circuit A that the circuit B is ready to perform communication with the circuit A. Further, the circuit B receives the value 0 output by the circuit A as the communication request signal Req at timing T0, and judges that there is no communication request from the circuit A.
Next, at timing T2, the circuit A outputs the value 1 as the communication request signal Req so as to notify the circuit B that there is a communication request, and outputs data to be transmitted D0 as the communication data signal Data. The circuit B outputs the value 1 as the communication response signal Ack also at timing T2 subsequent to timing T0.
Next, at timing T4, the circuit A receives the value 1 output by the circuit B as the communication response signal Ack at timing T2, and judges that the communication request and the data D0 are received. As a result, the circuit A outputs the value 0 as the communication request signal Req, and notifies the circuit B that there is no further communication request. At timing T4, the circuit B receives the communication request output by the circuit A as the communication request signal Req at timing T2, and receives the communication data D0. As a result, the circuit B outputs the value 0 as the communication response signal Ack, and notifies the circuit A that the circuit B cannot receive further communication.
Next, at timing T6, the circuit A again outputs the value 1 to the communication request signal Req so as to notify the circuit B that there is a communication request, and outputs data to be transmitted D1 as the communication data signal Data. The circuit B again outputs the value 1 to the communication response signal Ack, so as to notify the circuit A that the circuit B is ready to receive communication.
Next, at timing T8, the circuit A receives the value 1 output by the circuit B as the communication response signal Ack at timing T6, and judges that the communication request and the data D1 are received by the circuit B. As a result, the circuit A outputs the value 0 as the communication request signal Req, and notifies the circuit B that there is no further communication request. The circuit B receives the communication request output by the circuit A as the communication request signal Req at timing T6, and receives the communication data D1. As a result, the circuit B outputs the value 0 as the communication response signal Ack, and notifies the circuit A that the circuit B cannot receive further communication.
As described above, a handshake-type synchronous communication system in which the transmission-side circuit A and the reception-side circuit B communicate the communication request signal and the communication request signal each other (performing handshake to perform the synchronous communication) is widely used in an on-chip bus and the like.
On the other hand, an asynchronous system is used in a communication in which the frequency ratio of each clock of two circuits that communicate with each other is neither one to an integer nor an integer to one, or the phases of the two clocks are not equal to each other. When communication is performed using the asynchronous system, the timing at which the signal is output and the timing at which the signal is received are in the asynchronous relation, and the signal may be fluctuated between “0” and “1” for a certain period of time. This phenomenon is called metastability, which causes malfunction of the circuit. In the asynchronous system, a synchronizing circuit is typically used in order to prevent malfunction caused by metastability (e.g., patent document 1).
In the technique disclosed in the patent document 1, a synchronizing circuit is provided between a first circuit that performs a predetermined operation in synchronization with a first clock signal and a second circuit that performs a predetermined operation in synchronization with a second clock signal. This synchronizing circuit latches the output data from the first circuit in synchronization with the first clock signal, and outputs the latched signal in synchronization with the second clock signal.
Further, other technique than the one stated above is suggested for preventing malfunction due to metastability (e.g., patent document 2). The technique disclosed in the patent document 2 detects the change of a data input signal and a clock input signal and performs control not to change the signal of the data input of the flip-flop when the set up or the hold time is not satisfied, so as to prevent malfunction due to metastability.